In all electronic circuitry, there is a need to implement signal amplification schemes to obtain optimum signal gain as signals are propagated throughout the system. As an example of such a system, in large, high performance, very large scale integration (VLSI) chips or integrated circuits, an internal clock signal is distributed throughout the chip to control the timing of the chip as a function of an external system clock. Both the external clock signal and the chip-internal clock signal include a rising edge and a falling edge for every clock cycle. The internal clock cycle time is affected by several factors, each of which includes an associated signal propagation delay. The four cycle-affecting factors include storage devices on the chip, clock skew, logic evaluation and signal transmission. The term "clock skew" refers to the variation in clock or clock edge arrival time at various locations within a chip or integrated circuit. Clock "jitter" is another variable in a clock distribution network. Clock jitter refers to the variation in clock periodicity at a given location on a chip. The general term "clock uncertainty" is often used to include skew plus jitter. Of the four cycle-affecting factors, only the logic evaluation performs useful work and the other three factors are overhead that merely add to the cycle time.
The internal clock signal is typically generated from the external clock by a circuit called a clock buffer, and then distributed to the circuits on the chip through some form of on-chip clock distribution network. Ordinarily the clock buffer includes a large inverter that receives the external clock signal and transmits the internal clock signal to the on-chip clock distribution network. The distribution network may have one or more buffer/wiring layers.
It is advantageous to have the clock signal transition between voltage and ground as fast as possible. This entails producing an edge as fast as possible, while maintaining the time at which the edge rises and falls during each clock cycle. A clock edge is susceptible of providing a less accurate reference if the clock edge is slow. This is because noise is always superimposed on the clock. The noise artificially moves the edge position forward or backward in time by temporarily shifting the voltage on the clock distribution. If the edge transition can be made faster, the accuracy of the clock improves because faster clock transitions decrease noise generated clock skew. With less skew, more machine cycle time is available to perform useful logic at a given frequency.
Moreover, clock signal delay through clock buffers needs to be minimized for reduced skew and therefore improved performance. Increasing the number of gain-enhancing stages in a clock buffer normally has the effect of further delaying signal propagation through the buffer. The larger the delay through the clock distribution, the larger will be the skew due to process variation effects and the larger will be the jitter due to power supply variation effects. Thus there is a need to increase the gain of a clock buffer and optimize the gain per stage of the buffer so that circuit delay and clock uncertainty of a clock signal generated for application to a clock distribution circuit can be reduced.